1. Field of the Invention
The present invention relates generally to insulator layers within integrated circuits. More particularly, the present invention relates to methods for reducing the pattern sensitivity of ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layers within integrated circuits.
2. Description of the Related Art
As part of the evolutionary trend in semiconductor integrated circuit technology, there has been a continuing decrease in integrated circuit device and conductor element dimensions and a corresponding increase in aspect ratios of conductor elements which interconnect integrated circuit devices. Due to these decreases in conductor element dimensions and increases in conductor element aspect ratios, there is a continuing need for methods and materials through which there may be formed within integrated circuits insulator layers which possess excellent gap filling capabilities.
Recently developed within the art of insulator layers which possess excellent gap filling capabilities are silicon oxide insulator layers deposited upon patterned layers within integrated circuits through an ozone assisted Chemical Vapor Deposition (CVD) method. Silicon oxide insulator layers deposited through ozone assisted Chemical Vapor Deposition (CVD) methods are particularly efficient in forming void free gap filling silicon oxide insulator layers between dense high aspect ratio patterned conductor layers within integrated circuits.
Although silicon oxide insulator layers formed through ozone assisted Chemical Vapor Deposition (CVD) methods, in general, possess superb gap filling characteristics, such silicon oxide insulator layers are not without significant drawbacks. In particular, it is known in the art that ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layers typically exhibit a pattern sensitivity dependent upon the materials from which are formed the patterned substrate layers upon which are deposited the ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layers. The pattern sensitivity results from different deposition rates and/or different incubation times for forming ozone assisted Chemical Vapor Deposited silicon oxide insulator layers upon those different substrate layers.
Schematic cross-sectional diagrams of patterned integrated circuit layers which illustrate the results of the pattern sensitivity when forming upon the surfaces of those patterned integrated circuit layers an ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layer are shown in FIG. 1 and FIG. 2. Shown in FIG. 1 is a substrate layer 2 which is typically an insulator substrate layer formed of silicon oxide. Formed upon the substrate layer 2 is a pair of patterned stacks, typically patterned conductor stacks, which consist of patterned conductor layers 4a and 4b, beneath which reside patterned lower barrier layers 3a and 3b, respectively, and above which reside patterned upper barrier layers 5a and 5b, respectively. The patterned conductor layers 4a and 4b are typically formed of an aluminum containing alloy conductor and the patterned barrier layers 3a, 3b, 5a and 5b are typically formed of titanium nitride.
As shown in FIG. 1, a set of ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layers 8a, 8b and 8c, when formed within certain deposition conditions and parameters upon exposed portions of the substrate layer 2 and the patterned stacks, will exhibit decreasing deposition rates and increasing incubation times progressing from the substrate layer 2 to the patterned conductor layers 4a and 4b, and finally to the patterned upper barrier layers 5a and 5b. As also shown in FIG. 1, the ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layers 8a, 8b and 8c will not form upon the surfaces of the patterned upper barrier layers 5a and 5b until the incubation time for forming an ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layer upon the patterned upper barrier layers 5a and 5b layers has expired. Thus, resulting from the deposition rate differences and incubation time differences is a pattern sensitivity which is manifested as cusps where the ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layers 8a, 8b and 8c rise above but not upon the patterned upper barrier layers 5a and 5b.
Shown in FIG. 2 is a cross-sectional schematic diagram of an integrated circuit analogous to the cross-sectional diagram of the integrated circuit illustrated in FIG. 1, with the exception that a blanket conformal silicon oxide insulator layer 7 has been formed upon the exposed surfaces of the substrate layer 2 and the patterned stacks prior to forming the ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layers 8d, 8e and 8f thereupon. Notwithstanding the presence of the conformal silicon oxide insulator layer 7, a pattern sensitivity, although typically reduced, is still nonetheless observed when forming the ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layers 8d, 8e and 8f upon the conformal silicon oxide insulator layer 7. Analogously with the integrated circuit whose structure is illustrated in FIG. 1, the pattern sensitivity corresponds with the materials from which are formed the substrate layer 2 and the patterned stacks.
As a related phenomenon to the materials considerations through which pattern sensitivities within ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layers upon patterned layers within integrated circuits are derived, there also exists a patterned layer areal density phenomenon which simultaneously influences those pattern sensitivities. In particular it has been observed with respect to patterned layers formed of titanium nitride within integrated circuits that areal densities of the titanium nitride patterned layers in excess of about 50 percent provide patterned layers upon which are formed ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layers with substantially greater pattern sensitivities (ie: lower deposition rates and longer incubation times) than patterned titanium nitride layers of areal density less than about 40 percent.
Although the pattern sensitivities in forming ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layers upon patterned integrated circuit layers, such as patterned conductor layers, provide characteristics upon which several novel ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layer deposition processes may be based, the pattern sensitivities are often detrimental with regard to other ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layer deposition processes. In particular, the pattern sensitivities are detrimental when it is desired to form upon patterned layers within integrated circuits ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layers which possess uniformity across the patterned layer.
Thus, it is desirable in the art to provide methods for limiting the pattern sensitivity of ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layers upon patterned layers within integrated circuits. Particularly desirable in the art are methods through which pattern sensitivities derived from high areal density patterned layers may be limited. It is towards these goals that the present invention is directed.